The present invention relates to an output circuit of a logic circuit and, more particularly, to a circuit configuration of an emitter follower output circuit.
Generally, an emitter follower circuit of this kind is often used as an output circuit connected to the output side of a differential logic circuit constituted by a pair of differential transistors, so as to drive a load connected to a next stage.
In the following description, a circuit having such a combination of a differential logic circuit and an emitter follower output circuit as mentioned above will be referred to as an "ECL (Emitter Coupled Logic) circuit".
FIG. 1 shows a circuit diagram of an inverter circuit as an example of an ECL circuit using a conventional emitter follower output circuit.
This inverter circuit is constituted by a differential logic circuit 1 and an emitter follower output circuit 2.
The differential logic circuit 1 is basically constituted by a differential pair configuration of two NPN bipolar transistors Q.sub.1 and Q.sub.2. The NPN bipolar transistor Q.sub.1 has a base connected to an input terminal 3 and a collector connected to a higher potential power supply terminal 4 through a serially connected resistors R.sub.1 and R.sub.2. This transistor Q.sub.1 operates as an input transistor. The NPN bipolar transistor Q.sub.2 has a base connected to a reference potential supply terminal 5, and a collector connected to the higher potential power supply terminal 4 through the resistor R.sub.2. Emitters of the above two transistors Q.sub.1 and Q.sub.2 are connected together and commonly connected to a first lower potential power supply terminal 7 through a constant current source 6.
The emitter follower output circuit 2 is constituted by a constant current source 8 and an NPN bipolar transistor Q.sub.3 which operates as an output transistor. The NPN bipolar transistor Q.sub.3 has a collector connected directly to the higher potential power supply terminal 4, and an emitter connected to a second lower potential power supply terminal 9 through the constant current source 8.
An output signal from the differential logic circuit 1 is supplied to a base of the output NPN bipolar transistor Q.sub.3, and an output signal of the inverter circuit as a whole is outputted through an output terminal 10 connected to the emitter of the NPN bipolar transistor Q.sub.3.
A capacitor C.sub.L connected to the emitter of the output NPN bipolar transistor Q.sub.3 represents a capacitance acting as a load and including a wiring capacitance and a junction or coupling capacitance.
In the inverter circuit having such a configuration as described above, when a signal applied to the input terminal 3 has a high level potential, the NPN bipolar transistor Q.sub.1 becomes conductive, while the NPN bipolar transistor Q.sub.2 becomes non-conductive.
At this time, an output signal having a low level potential is outputted from the output terminal 10. This low level potential has a value obtained by subtracting, from the potential at the higher potential power supply terminal 4, the sum of the voltage drop across the series connection of the resistors R.sub.1 and R.sub.2 due to a current flowing through the constant current source 6 and the forward voltage across the base-emitter circuit of the output NPN bipolar transistor Q.sub.3.
Next, when the signal applied to the input terminal 3 has a low level potential, on the contrary, the input NPN bipolar transistor Q.sub.1 becomes non-conductive, and the NPN bipolar transistor Q.sub.2 becomes conductive.
At this time, therefore, the output signal outputted to the output terminal 10 has a high level potential. This high level potential has a value obtained by subtracting, from the potential at the higher potential power supply terminal 4, the sum of the voltage drop across the resistor R.sub.2 and the base-emitter forward voltage of the output NPN bipolar transistor Q.sub.3.
As described above, there generally exists in the ECL circuit a load capacitance C.sub.L at the output terminal 10 composed of wiring capacitances and junction capacitances of the output transistor Q.sub.3 and the constant current source 8.
Accordingly, there occurs charging/discharging of the load capacitance C.sub.L at the leading/trailing edge portions of the output signal.
Consideration is made on the ECL circuit using such a conventional emitter follower output circuit with respect to the charging/discharging of the load capacitance C.sub.L at the leading/trailing edge portions of the output signal.
In this case, at the leading edge portion of the output signal, the load capacitance C.sub.L is charged by a driving current flowing into the load capacitance C.sub.L from the output NPN bipolar transistor Q.sub.3. However, the driving capability of the transistor Q.sub.3 is so large that a sufficiently high response speed is obtained. Accordingly, there generates no problem irrespective of the current value of the constant current source 8.
At the trailing edge portion of the output signal, on the other hand, the load capacitance C.sub.L is discharged by the constant current source 8.
In order to make the response speed of the circuit high, it is therefore necessary to increase the current value of the constant current source 8.
Recently, integrated circuits have been made large-scaled so that the length of wiring becomes long to allow the load capacitance C.sub.L to become larger and larger. On the other hand, it is impossible to increase the current value of the constant current source correspondingly to the increase in the length of wiring, from the requirement of preventing an increase in power consumption. In the conventional emitter follower output circuit, therefore, there occurs a problem that the trailing time of the output signal becomes extremely long.